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This paper studies the realization ofthe high level synthesis from system behavioral (algorithmic orfunctional) description of circuits to structural description of RTL andlogic level. Based on Xilinx-FPGA library, the structural description ismapped to technology-dependent ASIC, and FPGA chips are generated. Themain points in this paper include the technical decision of eachsub-system in a VHDL high level synthesis system HLS/BIT. The system isrealized on SUN SPARC 2, and correct running results are given.