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宽带信号的高速采集电路是超宽带(ultra-wideband,UWB)通信系统的基本单元,在满足高速采集要求的同时保持低功耗是设计的难题。该文通过改进全差分预放和高速比较器电路,设计了一个用于超宽带的4 b flash模数转换器(ADC),获得了2 GHz的采样速率,而功耗仅为38mW。基于和舰0.18μm CMOS工艺的仿真设计和流片测试结果表明,该ADC最大积分非线性(INL)和微分非线性(DNL)指标分别为+0.31/-0.28 LSB和+0.53/-0.36LSB;采样率在600 MHz以内时非杂散动态范围(SFDR)大于38 dB。所设计的ADC核心面积小于0.14 mm2。
High-speed broadband signal acquisition circuit is the basic unit of ultra-wideband (UWB) communication system. To meet the high-speed acquisition requirements while maintaining low power consumption is a design challenge. By improving the fully differential preamplifier and high-speed comparator circuits, a 4 b flash analog-to-digital converter (ADC) for ultra-wideband is designed to achieve a 2 GHz sampling rate while consuming only 38 mW. Simulation results and strip test results based on Hezuo 0.18μm CMOS technology show that the maximum integral nonlinearity (INL) and differential nonlinearity (DNL) of the ADC are + 0.31 / -0.28 LSB and + 0.53 / -0.36LSB, respectively. Spurious-Free Dynamic Range (SFDR) is greater than 38 dB at sample rates below 600 MHz. The designed ADC core area is less than 0.14 mm2.