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针对ASIC芯片设计中时钟树综合效率和时序收敛的问题,提出了一种高效的时钟树综合方法,特别适用于现代先进深亚微米工艺中的高集成度、高复杂度的设计中。改进了传统时钟树综合方法,通过采用由下至上逐级分步综合的方法实现。该设计方法在SMIC 0.18μm eflash工艺下的一款电力线载波通信芯片中成功流片验证,结果表明分步综合能够在实现传统设计功能的前提下,在完成时序收敛时有效减少不必要的器件插入,从而减小芯片面积,降低整体功耗,有效改善绕线拥塞度。
In order to solve the problem of clock tree synthesis efficiency and timing closure in ASIC chip design, an efficient clock tree synthesis method is proposed, which is especially suitable for the highly integrated and highly complex design of modern advanced deep sub-micron technology. Improved the traditional clock tree synthesis method, through the use of bottom-up step by step synthesis method. The design method is successfully verified in a power line carrier communication chip under the SMIC 0.18μm eflash process. The results show that the step-by-step synthesis can effectively reduce unnecessary device insertion when the timing closure is achieved under the premise of realizing the traditional design functions , Thereby reducing the chip area, reducing the overall power consumption, effectively improve the winding congestion.