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提出了一种新的闩锁型比较器结构。由于它的低kickback噪声特性,此比较器特别适合应用于差分模拟-数字转换器(ADCs)。电路采用标准0·35μm的工艺进行模拟,结果显示此比较器在3.3V电源下采样频率为400Ms/s,并且kickback噪声比传统结构减少了88%。
A new latch-type comparator structure is proposed. Due to its low kickback noise characteristics, this comparator is particularly suitable for use in differential analog-to-digital converters (ADCs). The circuit was simulated using a standard 0.35 μm process and the results showed that this comparator has a sampling frequency of 400Ms / s at 3.3V and a kickback noise reduction of 88% over the conventional structure.