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描述了多级滤波图像处理ASIC芯片的体系结构,针对该芯片的数据缓冲存储问题,通过控制模块对一个输入FIFO和三个输出FIFO的协调控制,高效地实现了多路数据的实时处理和传输。结合应用要求,一个异步FIFO对输入数据缓冲存储,使快速数据通道与慢速数据输入相匹配;三个同步FIFO,分别对应单级1×3、两级1×3级联(相当于1×5)和三级1×3级联(相当于1×7)滤波模板的图像数据输出缓存,分时复用一路输出总线。仿真结果表明设计是正确且有效的。
In this paper, the architecture of multi-stage filter ASIC chip is described. According to the data buffer storage of the chip, the control module realizes the multi-channel data real-time processing and transmission through the coordinated control of one input FIFO and three output FIFOs . In combination with the application requirements, an asynchronous FIFO buffers the input data so that the fast data channel matches the slow data input. Three synchronous FIFOs, corresponding to a single stage of 1 × 3 and two stages of 1 × 3 cascades (equivalent to 1 × 5) and three 1 × 3 cascade (equivalent to 1 × 7) filter template image data output buffer, time-multiplexed all the way to the output bus. Simulation results show that the design is correct and effective.