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In this paper we discuss a novel storage scheme for simultaneous memory access in parallel turbo decoder.The new scheme employs vertex coloring in graph theory.Compared to a similar method that also uses unnatural order in storage, our scheme requires 25 more memory blocks but allows a simpler configuration for variable sizes of code lengths that can be implemented on-chip.Experiment shows that for a moderate to high decoding throughput (40～100 Mbps),the hardware cost is still affordable for 3GPP’s (3rd generation partnership project) interleaver.
In this paper we discuss a novel storage scheme for simultaneous memory access in parallel turbo decoder. New scheme employs vertex coloring in graph theory. Compared to a similar method that also uses unnatural order in storage, our scheme requires 25 more memory blocks but allows a simpler configuration for variable sizes of code lengths that can be implemented on-chip .Experiment shows that for a moderate to high decoding throughput (40-100 Mbps), the hardware cost is still affordable for 3GPP’s (3rd generation partnership project) interleaver.