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为满足现代雷达的高性能应用需求,文中提出并设计了一种可重构专用处理(RASP)架构。其采用非规则化微结构和混合重构策略,有效提升了并行流水计算的性能;通过兵乓处理机制掩盖DDR读写时间,充分发挥了运算资源的效率。RASP作为硬件加速核嵌入华睿2号DSP芯片并于TSMC 40 nm工艺下完成流片。测试结果显示,RASP完成1 K(1 024)点FFT的运算时间为2.57μs,处理效率高达42%,相比于NoC、MorphoSys、C6678、T4240等处理器,性能提升至1.9~30倍,效率达到1.25~4倍。
In order to meet the high-performance applications of modern radar, a Reconfigurable Application Specific Processing (RASP) architecture is proposed and designed. It adopts non-regularized microstructure and hybrid reconstruction strategy to effectively improve the performance of parallel pipeline computation. By using a mask-based processing mechanism to mask the read and write time of DDR, it can fully utilize the computing resource efficiency. RASP as a hardware acceleration core embedded Hua Rui No. 2 DSP chip and TSMC 40 nm process to complete the film. The test results show that the RASP completes 1K (1 024) point FFT operation time 2.57μs, processing efficiency up to 42%, compared to NoC, MorphoSys, C6678, T4240 and other processors, performance increased to 1.9 to 30 times, efficiency Reached 1.25 to 4 times.