In reconfigurable system,fast reconfiguration and small size of configuration contexts are strongly required to enhance the processing performance and reduce the implementation overhead.In this paper,a hierarchical representation of contexts for CGRA called HCC is proposed to satisfy the above requirements.In HCC,the contexts are constructed in a hierarchical fashion to thoroughly eliminate the repetitive portions of the contexts,not only reducing the overall contexts storage size,but also alleviating the contexts transportation overhead.The fast context-indexing mechanism is proposed in HCC to achieve high configuration speed,since the hierarchically organized contexts can be located and accessed conveniently.HCC has been verified in a reconfigurable processor called REMUS HP.Owing to HCC,when implementing H.264 decoding on REMUS HP,76.67%of the overall contexts are reduced compared with the traditional non-hierarchical one;and the configuration speed is averagely 23×increased compared with the latest reported optimized configuration mechanism on Virtex-4 FX60.REMUS HP is implemented on a 48.9 mm2silicon with TSMC 65 nm technology.Simulation shows that 1920×1088@30 fps could be achieved for H.264 high-profile decoding when exploiting a 200 MHz working frequency.Compared with the high performance version of XPP,the performance is 181%boosted. In reconfigurable system, fast reconfiguration and small size of configuration contexts are strongly required to enhance the processing performance and reduce the implementation overhead.In this paper, a hierarchical representation of contexts for CGRA called HCC is proposed to satisfy the above requirements.In HCC, the contexts are constructed in a hierarchical fashion to completely eliminate the repetitive portions of the contexts, not only reducing the overall contexts storage size, but also alleviating the contexts transportation overhead. the fast context-indexing mechanism is proposed in HCC to achieve high configuration speed , since the hierarchically organized contexts can be located and accessed conveniently. HCC has been verified in a reconfigurable processor called REMUS HP. Out to HCC, when implemented H.264 decoding on REMUS HP, 76.67% of the overall contexts are reduced compared with the traditional non-hierarchical one; and the configuration speed is averagely 23 × increased compar ed with the latest reported optimized configuration mechanism on Virtex-4 FX60. REMUS HP is implemented on a 48.9 mm2 silicon with TSMC 65 nm technology. Simulation shows that 1920 × 1088 @ 30 fps could be achieved for H.264 high-profile decoding when exploiting a 200 MHz working frequency. Compared with the high performance version of XPP, the performance is 181% boosted.