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研究了基于IBM 8RF 130 nm工艺部分耗尽绝缘体上Si(PDSOI)动态阈值晶体管(DTMOS)体电阻、体电容以及体电阻和体电容乘积(体延迟)随Si膜厚度和器件宽度的变化。结果表明,Si膜厚度减小会导致体阻增大、体电容减小,但是体电阻和体电容的乘积却明显增大。Si膜厚度从200 nm减小到80 nm,体延迟增加将近两个数量级。器件宽度增加使得体电阻和体电容都明显增大,DTMOS电路延迟也因此指数递增。推导出了PDSOI DTMOS的延迟模型,为SOI DTMOS器件设计提供了参考。
The body resistance, body capacitance, body resistance and body capacitance product (bulk delay) with the Si film thickness and device width of PDOI dynamic threshold transistor (DTMOS) are studied based on IBM 8RF 130 nm process. The results show that the decrease of Si film thickness leads to the increase of body resistance and decrease of body capacitance, but the product of body resistance and body capacitance increases obviously. Si film thickness decreased from 200 nm to 80 nm, the bulk retardation increased by nearly two orders of magnitude. The increase of the width of the device makes the body resistance and body capacitance all increase obviously, so the delay of DTMOS circuit therefore increases exponentially too. The delay model of PDSOI DTMOS is deduced, which provides a reference for SOI DTMOS device design.