A novel silicon-on-insulator(SOI) power metal-oxide-semiconductor Held effect transistor with an interface-gate(IG SOI) structure is proposed,in which the trench polysilicon gate extends into the buried oxide layer(BOX)at the source side and an IG is formed.Firstly,the IG offers an extra accumulation channel for the carriers.Secondly,the subsidiary depletion effect of the IG results in a higher impurity doping for the drift region.A low specific on-resistance is therefore obtained under the condition of a slightly enhanced breakdown voltage for the IG SOI.The influences of structure parameters on the device performances are investigated.Compared with the conventional trench gate SOI and lateral planar gate SOI,the specific on-resistances of the IG SOI are reduced by 36.66%and 25.32%with the breakdown voltages enhanced by 2.28%and 10.83%at tie same SOI layer of3μm,BOX of 1 μm,and half-cell pitch of 5.5 μm,respectively. A novel silicon-on-insulator (SOI) power metal-oxide-semiconductor Held effect transistor with an interface-gate (IG SOI) structure is proposed, in which the trench polysilicon gate extends into the buried oxide layer (BOX) at the source First and the IG are formed. Firstly, the IG offers an extra accumulation channel for the carriers. Secondarily, the subsidiary depletion effect of the IG results in a higher impurity doping for the drift region. A low specific on-resistance is therefore obtained under the condition of a slightly enhanced breakdown voltage for the IG SOI. These influences of structure parameters on the device performances are investigated. Compared with the conventional trench gate SOI and lateral planar gate SOI, the specific on-resistances of the IG SOI are reduced by 36.66% and 25.32% with the breakdown voltages enhanced by 2.28% and 10.83% at the same SOI layer of 3 μm, BOX of 1 μm, and half-cell pitch of 5.5 μm, respectively.