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研究基于 VME总线 SHARC并行处理系统的设计与实现 .系统采用 SHARC处理器的 L INK口组成网状并行处理结构 ;VME总线接口采用芯片 VIC6 4和 EPLD实现 ;信号互连采用传输线结构 ,用适当的端接技术与合理的布局抑制信号反射和串扰 ,并进行了信号完整性分析和仿真 .单块 SHARC信号处理板具有 9.6× 10 8次 /s浮点运算 ,32 0 MB/s数据传输能力和 VME总线主 /从操作能力 ,并支持中断管理和总线仲裁 ,可组成1.0× 10 10 次 /s浮点运算能力的信号处理系统 .
Research on the design and implementation of SHARC parallel processing system based on VME bus.The system uses SHARC processor’s L INK port to form a network parallel processing structure; VME bus interface using chip VIC6 4 and EPLD; signal interconnection using transmission line structure, with the appropriate The termination technology and reasonable layout suppress the signal reflection and crosstalk, and analyze and simulate the signal integrity. The single SHARC signal processing board has 9.6 × 10 8 floating-point operations per second and 32 0 MB / s data transfer capability VME bus master / slave operation capability, and supports interrupt management and bus arbitration, can form a 1.0 × 10 10 times / s floating-point computing power signal processing system.