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磷化铟汽相外延已用于沉积制备 FET 所需的亚微米多层结构。该结构是沉积在绝缘掺铁衬底上,由缓冲层、表面沟道层和 n~(++)接触层组成。缓冲层之 N_d-N_d<10~(14)cm~(-3)、μ_(77°K)>50,000cm~2/v·s。表面沟道层掺硫,其厚度为0.3～0.5μm,载流子浓度控制在8×10~(16)cm~(-3)到2×10~(17)cm~(-3),相应的298°K 电子迁移率为3900cm~2/v·s 和3000cm~2/v·s,并且没有观察到性能随沟道层的减薄而退化的现象。由于材料具有极好的横向均匀性,从而用实验证明了生长 n~(++)层能使接触电阻减少以及采用隐埋沟道能引起栅的改善。发展了用于测量载流子浓度分布的金属-氧化物-半导体技术,当FET 的沟道掺杂浓度为2×10~(17)cm~(-3)时,用这种技术能提供6000(?)的耗尽。
Indium Phosphide vapor phase epitaxy has been used to deposit the sub-micron multi-layer structures needed to fabricate FETs. The structure is deposited on an insulating doped iron substrate and consists of a buffer layer, a surface channel layer and an n ~ (++) contact layer. The N_d_N_d of the buffer layer is less than 10 ~ (14) cm ~ (-3), μ_ (77 ° K)> 50,000cm ~ 2 / v · s. The surface channel layer doped with sulfur has a thickness of 0.3-0.5 μm and a carrier concentration of 8 × 10-16 cm -3 to 2 × 10 17 cm -3. Correspondingly, The 298 ° K electron mobility was 3900 cm -2 / v · s and 3000 cm -2 / v · s, and no deterioration of the performance with the thinning of the channel layer was observed. Due to the excellent lateral uniformity of the material, experiments have proven that growth of n ~ (++) layers can result in reduced contact resistance and the use of buried trenches can lead to gate improvements. The metal-oxide-semiconductor technology for the measurement of carrier concentration has been developed. When the channel doping concentration of the FET is 2 × 10 ~ (17) cm ~ (-3), this technique can provide 6000 (?) Depleted.