A 13-bit 8 MSample/s high-accuracy CMOS pipeline ADC is proposed. At the input,the sample-and- hold amplifier (SHA) is removed for low power and low noise; meanwhile,an improved sampling circuit is adopted to alleviate the clock skew effect. On-chip bias current is programmable to achieve low power dissipation at different sampling rates. Particularly,drain-to-source voltages in the operational amplifiers (opamps) are fixed to ensure high DC gain within the variant range of the bias current. Both on-chip and off-chip decoupling capacitors are used in the voltage reference circuit in consideration of low power and stability. The proposed ADC was implemented in 0.18-μm 1P6M CMOS technology. With a 2.4-MHz input,the measured peak SNDR and SFDR are 74.4 and 91.6 dB at 2.5 MSample/s,74.3 and 85.4 dB at 8.0 MSample/s. It consumes 8.1,21.6,29.7,and 56.7 mW (including I/O drivers) when operating at 1.5,2.5,5.0,and 8.0 MSample/s with 2.7 V power supply,respectively. The chip occupies 3.2 mm2,including I/O pads. A the 13-bit 8 MSample / s high-accuracy CMOS pipeline ADC is proposed. At the input, the sample-and-hold amplifier (SHA) is removed for low power and low noise; meanwhile, an improved sampling circuit is adopted to alleviate Particularly, drain-to-source voltages in the operational amplifiers (opamps) are fixed to ensure high DC gain within the variant range of the bias current. Both on-chip and off-chip decoupling capacitors are used in the voltage reference circuit in consideration of low power and stability. The proposed ADC was implemented in 0.18-μm 1P6M CMOS technology. With a 2.4-MHz input, the measured Peak SNDR and SFDR are 74.4 and 91.6 dB at 2.5 MSample / s, 74.3 and 85.4 dB at 8.0 MSample / s. It consumes 8.1, 21.6, 29.7, and 56.7 mW including I / O drivers when operating at 1.5, 2.5, 5.0, and 8.0 MSample / s with 2.7 V power supply, respectively. The chip occupies 3.2 mm2, i ncluding I / O pads.