This paper presents a 10 bit successive approximation register(SAR) analog-to-digital converter(ADC)in 0.18 m 1P6 M CMOS technology with a 1.8 V supply voltage. To improve the conversion speed, a partial split capacitor switching scheme is proposed. By reducing the time constant of the bit cycles, the proposed technique shortens the settling time of a capacitive digital-to-analog converter(DAC). In addition, a new SAR control logic is proposed to reduce loop delay to further enhance the conversion speed. At 1.8 V supply voltage and 50 MS/s the SAR ADC achieves a signal-to-noise and distortion ratio(SNDR) of 57.5 d B and spurious-free dynamic range(SFDR) of 69.3 d B. The power consumption is 2.26 m W and the core die area is 0.096 mm~2. This paper presents a 10 bit successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18 m 1P6 M CMOS technology with a 1.8 V supply voltage. To improve the conversion speed, a partial split capacitor switching scheme is proposed. By reducing the time constant of the bit cycles, the proposed technique shortens the settling time of a capacitive digital-to-analog converter (DAC). In addition, a new SAR control logic is proposed to reduce the loop delay to further enhance the conversion speed At 1.8 V supply voltage and 50 MS / s the SAR ADC achieves a signal-to-noise and distortion ratio (SNDR) of 57.5 d B and spurious-free dynamic range (SFDR) of 69.3 d B. The power consumption is 2.26 m W and the core die area is 0.096 mm ~ 2.