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介绍了工作在 1.8V的 8位 12 5 MHz流水线 A/ D转换器 .采用了低功耗的增益自举单级折叠级联运放 ,器件尺寸逐级减小进一步优化功耗 .为消除不匹配造成的相位遗漏与重叠 ,每级均有独立的双相不交叠时钟发生电路 ,并由一全局的时钟树驱动 .输入频率为 6 2 MHz的信号 ,以 12 5 MHz时钟采样 ,可获得 4 9.5 d B(7.9位有效精度 )的信号与噪声及谐波失真比 (SNDR) ,功耗仅为 71m W.电路用 0 .18μm CMOS工艺实现 ,面积为 0 .4 5 m m2 .
An 8-bit, 125 MHz, pipeline A / D converter operating at 1.8V is presented with a low-power, gain-boosted, single-stage folded cascaded op amp that reduces step-by-step device size to further optimize power consumption. Phase mismatch and overlap caused by matching, each stage has an independent biphasic non-overlapping clock generation circuit and driven by a global clock tree Input signal frequency of 6 2 MHz, with 12 5 MHz clock sampling available The signal-to-noise and harmonic distortion ratio (SNDR) of 4 9.5 d B (7.9-bit effective precision) consumes only 71m W. The circuit is implemented in a 0.18μm CMOS process and has an area of 0.45 m square meters.