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在评估模数转换器(ADC)性能时，利用锁相环（PLL）内部的频率合成器，我们可以重现价格昂贵的实验室测试系统中相干测试设备所测试的电路性能。这种测试系统能获得超过10MHz的采样速率。PLL时钟性能可以充分满足采样速率为140kHz的14位系统。一个相干系统不同于实际的采样数据?
In evaluating the performance of an analog-to-digital converter (ADC), we can reproduce the circuit performance tested by coherent test equipment in expensive laboratory test systems using a frequency synthesizer internal to a phase-locked loop (PLL). This test system can get more than 10MHz sampling rate. PLL clock performance can fully meet the 14-bit system sampling rate of 140kHz. A coherent system is different from the actual sampling data?