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为了满足微电子器件不断扩展到更小尺寸的需求,SiO_2栅极介电层被高介电常量材料Hf(Zr)O_2所替代,以尽可能减少流过介电薄膜的漏电流。然而,与高介电常量(高κ)电介质连接时,传统Si通道中的电子迁移率由于库仑散射、表面粗糙度散射、远程声子散射和介电电荷捕获而有所下降。Ⅲ-Ⅴ和Ge是两个有希望的候选材料,其迁移率均优于Si。尽管如此,与Si基界面相比,Hf(Zr)O_2/Ⅲ-Ⅴ(Ge)的界面结合更为复杂。成功制造高质量器件关键在于优化器件界面设计时对Hf(Zr)O_2/Ⅲ-Ⅴ(Ge)界面结合结构的理解与设计。因此,从原子尺度准确了解界面结合与界面态形成的机制变得尤为重要。在本文中,笔者利用第一性原理计算方法,对HfO_2与GaAs之间的界面性质进行了研究。结果表明,隙间态主要由As-As二聚物键合、Ga部分氧化(在3+和1+之间)和Ga-悬挂键贡献。这些研究成果能为最优化界面钝化提供重要的指导意见。
In order to meet the ever-increasing demand for smaller electronic devices, SiO 2 gate dielectric is replaced by high dielectric constant Hf (Zr) O 2 to minimize the leakage current flowing through the dielectric film. However, the electron mobility in traditional Si channels decreases with Coulomb scattering, surface roughness scattering, long-range phonon scattering and dielectric charge trapping when connected to high-k (high-κ) dielectrics. III-V and Ge are two promising candidate materials with better mobility than Si. Nevertheless, the interfacial bonding of Hf (Zr) O 2 / III-V (Ge) is more complicated than that of Si-based. The key to successful fabrication of high quality devices lies in the understanding and design of the interface structure of the Hf (Zr) O_2 / Ⅲ-Ⅴ (Ge) interface at the time of device interface design optimization. Therefore, it is particularly important to understand accurately the mechanism of interface bonding and interface state formation from the atomic scale. In this paper, I use first-principles calculations to study the interface between HfO_2 and GaAs. The results show that interstitial states are mainly composed of As-As dimers, Ga partial oxidation (between 3+ and 1+) and Ga-dangling bonds. These findings provide important guidance for optimizing passivation of interfaces.