提出了一种先进的双多晶硅非自对准NPN管的器件结构,并实际用于一种高性能NPN管的研制。该器件结构主要通过多晶外基区减小基区电阻和基区结面积,以及使用SIC技术减小集电极电阻的方式,极大地提升了NPN管的特征频率。通过实际工艺流片验证,实现了BVCEO=5.6 V、fT=13.5 GHz的高速NPN管。该器件结构较双多晶自对准器件结构易于加工,可以广泛用于其他高速互补双极器件的研制。 An advanced dual-polysilicon NPN transistor device structure is proposed and is actually used for the development of a high-performance NPN transistor. The structure of the device greatly improves the characteristic frequency of the NPN transistor by reducing the base resistance and the base junction area through the polycrystalline outer base region and reducing the collector resistance by using the SIC technique. Through the actual process flow sheet validation, a high speed NPN tube with BVCEO = 5.6 V and fT = 13.5 GHz was realized. The structure of the device is easier to process than that of the dual polycrystalline self-aligned device and can be widely used for the development of other high-speed complementary bipolar devices.