4.晶体管十进分频与晶体管十进计数器的设计: (1) 由于振荡器的振荡频率较高,因此,本仪器采用了三级十进计数分频电路,每级由四个双稳态电路构成,双稳态电路采用比较灵敏的基极负脉冲触发形式。四级双稳态电路是串接的(见图14)。第一级双稳态电路,每输入二个触发脉冲翻转一次,每翻转二次向第二级双稳电路输出一只触发脉冲,使第二级双稳电路同时翻转一次。当输入第4个脉冲时。第2级双稳态翻转二次,同时向第3级双稳电路输出一只触发脉冲,使 4. Transistor decade and transistor decade counter design: (1) As the oscillation frequency of the oscillator is high, therefore, the instrument uses a three-decade counter divider circuit, each stage consists of four bistable Circuit, bistable circuit using a more sensitive base negative pulse trigger form. Four-stage bistable circuits are connected in series (see Figure 14). The first stage of the bistable circuit, each input two flip-flops once, each flip two times to the second stage of a bistable output pulse trigger, so that the second flip-flops bounce circuit at the same time. When the 4th pulse is input. Level 2 bistable flip second, at the same time to the level 3 bistable circuit output a trigger pulse