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设计了一种应用于CMOS D类音频功率放大器的PWM高速比较器。输入级为Rail-to-Rail结构,中间级由锁存器和自偏置差分放大器组成,输出级为反相器结构。由于采用了锁存器和自偏置放大器结构,比较器可以在很短的时间内驱动大电容,满足后续电路对驱动能力的要求。基于CSMC 0.5μm CMOS工艺的BSIM3V3Spice模型,采用Hspice对PWM比较器进行仿真。结果表明,在典型模型下,比较器的电源抑制比为56dB,直流开环增益为45dB,输入共模范围(ICMR)为-0.19～4.93V,传输延时为15ns。
A PWM high speed comparator for CMOS class D audio power amplifier is designed. The input stage is a Rail-to-Rail configuration. The middle stage consists of a latch and a self-biased differential amplifier. The output stage is an inverter configuration. Due to the latch and self-bias amplifier structure, the comparator can drive a large capacitor in a very short period of time, to meet the follow-up circuit requirements of the drive capability. Based on BSMC3V3Spice model of CSMC 0.5μm CMOS process, Hspice was used to simulate PWM comparator. The results show that the comparator has a power rejection ratio of 56dB, a dc open-loop gain of 45dB, an input common-mode range (ICMR) of -0.19 to 4.93V and a propagation delay of 15ns in a typical model.