介绍了一个通过4片250MSps的高速ADC交替采样实现高达1GSps数据采集系统实现方案,对关键部分的采样时钟系统设计进行了重点讨论,详细介绍了基于Spantan-3AFPGAODDR2技术的采样时钟系统实现方法;给出了多通道数据接收和同步的实现方案,对硬件实现的关键点给出了建议和说明;整个系统硬件方案简洁、性能稳定、且实现成本非常低廉;对系统的性能测试表明其有效位数高于6比特,满足实际应用的需求,适合于高速数字信号获取及处理等领域。 This paper introduces a scheme to realize data acquisition system of up to 1GSps by alternately sampling four 250MSps high speed ADCs. The key part of sampling clock system design is discussed in detail. The realization of sampling clock system based on Spantan-3AFPGAODDR2 technology is introduced in detail. Out of multi-channel data reception and synchronization of the program, the hardware implementation of the key points are given recommendations and instructions; the entire system hardware solution is simple, stable performance, and the cost is very low; the performance of the system tests show that the effective median Higher than 6 bits to meet the needs of practical applications, suitable for high-speed digital signal acquisition and processing and other fields.