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Two essential blocks for the PLLs based on CP, a phase-frequency detector(PFD) and an improved current steering charge-pump(CP), are developed. The mechanisms for widening the phase error detection range and eliminating the dead zone are analyzed and applied in our design to optimize the proposed PFD. To obtain excellent current matching and minimum current variation over a wide output voltage range, an improved structure for the proposed CP is developed by fully utilizing many additional sub-circuits. Implemented in a standard 90-nm CMOS process, the proposed PFD achieves a phase error detection range from –354° to 354° and the improved CP demonstrates a current mismatch of less than 1.1% and a pump-current variation of 4% across the output voltage,swinging from 0.2 to 1.1 V, and the power consumption is 1.3 m W under a 1.2-V supply.
Two essential blocks for the PLLs based on CP, a phase-frequency detector (PFD) and an improved current steering charge-pump (CP), are developed. The mechanisms for widening the phase error detection range and eliminating the dead zone are analyzed and applied in our design to optimize the proposed PFD. To obtain an excellent current matching and minimum current variation over a wide output voltage range, an improved structure for the proposed CP is developed by fully supporting many additional sub-circuits. Implemented in a standard 90- nm CMOS process, the proposed PFD achieves a phase error detection range from -354 ° to 354 ° and the improved CP demonstrates a current mismatch of less than 1.1% and a pump-current variation of 4% across the output voltage, swinging from 0.2 to 1.1 V, and the power consumption is 1.3 m W under a 1.2-V supply.