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定点尾数乘除法器是相应32位浮点运算的核心部件,针对工控应用,本文采用半定制方法完成了设计并且采用TSMC0.18微米工艺实现.乘法器采用基4Booth编码,通过对符号位、隐含位的处理减少了部分积的生成,并在Wallace树求和过程中,引入4:2压缩器,加快了求和速度.除法器采用改进的SRT算法,引入商位猜测、部分余并行计算、商位修正值选择电路.乘除法器均采用了进位保留加法器提高运算速度.后端物理实现表明,乘除法器的频率分别可到227MHz,305MHz,整体设计具有简洁、快速、计算准确的特征.
Fixed-point mantissa multiplication and division is the corresponding 32-bit floating-point arithmetic core components, for industrial applications, this paper uses a semi-custom method to complete the design and the use of TSMC0.18 micron technology.Based on 4Booth encoder multiplication, through the sign bit, hidden The inclusion process reduces the generation of partial products, and the 4: 2 compressor is introduced to speed up the summation during the Wallace tree summing process. The divider adopts the improved SRT algorithm, the introduction of quotient position estimation and the partial remainder parallel computation , Quotient correction value selection circuit multiply and divide are used to carry a carry adder to improve the computing speed.Realization of the physical implementation shows that the frequency divider can be 227MHz, 305MHz, the overall design is simple, fast, accurate calculation feature.