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本文建立在逻辑电路内部自测试的基础上，提出了一种新的缩短伪随机测试序列长度的方法。文中首先找到了最难测故障在电路中的分布，建立了对应于最难测故障的电路模型，然后用线性反馈移位寄存器对这些电路模型的输出信号进行压缩，通过分析压缩后的特征码，得出最难测故障的测试长度。最后利用电路的原始输入概率与测试长度之间的关系，提出了一种缩短测试序列长度的算法，求出了最短的测试长度与最佳的输入概率。
Based on the internal self-test of logic circuits, this paper proposes a new method to shorten the length of pseudo-random test sequences. First of all, the distribution of the most unpredictable faults in the circuit is found, and the circuit model corresponding to the most unpredictable fault is established. Then the linear feedback shift register is used to compress the output signals of these circuit models. , Come to the test of the most difficult fault length. Finally, by using the relationship between the original input probabilities of the circuit and the test length, an algorithm to shorten the length of the test sequence is proposed. The shortest test length and the best input probability are obtained.