A simple process flow method for the fabrication of poly-Si nanowire thin film transistors(NW-TFTs) without advanced lithographic tools is introduced in this paper.The cross section of the nanowire channel was manipulated to have a parallelogram shape by combining a two-step etching process and a spacer formation technique.The electrical and temperature characteristics of the developed NW-TFTs are measured in detail and compared with those of conventional planar TFTs(used as a control).The as-demonstrated NW-TFT exhibits a small subthreshold swing(191 mV/dec),a high ON/OFF ratio(8.5 × 10~7),alow threshold voltage(1.12 V),a decreased OFF-state current,and a low drain-induced-barrier lowering value(70.11 mV/V).The effective trap densities both at the interface and grain boundaries are also significantly reduced in the NW-TFT.The results show that all improvements of the NW-TFT originate from the enhanced gate controllability of the multi-gate over the channel. A simple process flow method for the fabrication of poly-Si nanowire thin film transistors (NW-TFTs) without advanced lithographic tools is introduced in this paper. The cross section of the nanowire channel was manipulated to have a parallelogram shape by combining a two- step etching process and a spacer formation technique. electrical and temperature characteristics of the developed NW-TFTs are measured in detail and compared with those of conventional planar TFTs (used as a control). as-demonstrated NW-TFT exhibits a small subthreshold (191 mV / dec), a high ON / OFF ratio (8.5 × 10 -7), alow threshold voltage (1.12 V), a decreased OFF-state current, and a low drain-induced-barrier lowering value /V).The effective trap densities both at the interface and the grain boundaries are also significantly reduced in the NW-TFT.The results show that all improvements of the NW-TFT originate from the enhanced gate controllability of the multi-gate over the channel .