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随着存储系统的访问速度与处理器运算速度的差距越来越显著,访存性能已成为提高处理器性能的瓶颈.通过对程序的访存行为进行分析,提出快速地址计算的自适应栈高速缓存方案.该方案将栈访问从数据高速缓存的访问中分离出来,充分利用栈空间数据访问的特点,提高指令级并行度,减少数据高速缓存污染,降低数据高速缓存失效率,并采用快速地址计算策略,减少栈访问的命中时间.该栈高速缓存在发生栈溢出时能够自适应地关闭,以避免栈切换对处理器性能的影响.栈高速缓存标志中增加进程标识,进程切换时不需要将数据写到低层存储系统中,适用于多进程环境.SPEC CPU2000程序运行结果表明,采用快速地址计算的自适应栈高速缓存方案,25.8%的访存指令可以并行执行,数据高速缓存失效率平均降低9.4%,IPC值平均提高6.9%.
As the difference between storage system access speed and processor operation speed becomes more and more significant, the storage performance has become a bottleneck to improve the processor performance.Based on the analysis of the program’s memory access behavior, this paper proposes a fast address calculation of adaptive stack speed This scheme separates stack access from data cache access, makes full use of the characteristics of stack space data access, improves instruction level parallelism, reduces data cache pollution, reduces data cache failure rate and adopts fast address Computing strategy to reduce the hit time of stack access.The stack cache can be adaptively closed in the event of a stack overflow to avoid the impact of the stack switch on the processor performance.The process identifier is added to the stack cache flag and not required for process switching The data is written to the low-level storage system, suitable for multi-process environment.SPEC CPU2000 program results show that the use of fast address calculation of the adaptive stack caching scheme, 25.8% of the memory access instructions can be executed in parallel, the average data cache failure rate A 9.4% decrease and an IPC increase of 6.9% on average.