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在研究超长指令 (VL IW,Very L ong Instruction Word)体系结构的基础上 ,总结了 VL IW体系结构的指令结构特征、处理器结构体征和执行特征 ,用VL IW的编译调度很好的提高了指令级的并行处理。提高指令级并行性是实现高性能中央处理器的主要手段 ,因而如何实现指令的动态调度和解决控制相关以及多指令流出 ,这就成为了开发一个指令级并行性能高的微处理器的关键所在。文中介绍了 VL IW的循环展开的指令处理技术 ,大大提高了指令的执行速度 ,从一个方面预示了 VL IW的发展前景。
Based on the research of VLIW (Very Long Instruction Word) architecture, the VLIW architecture instruction structure features, processor architecture signatures and execution features are summarized, and the VLIW compile scheduling is well improved Instruction-level parallel processing. Improving instruction-level parallelism is the primary means of implementing high-performance CPUs. Therefore, how to achieve dynamic scheduling of instructions and control-related and multi-instruction outflows has become the key to developing an instruction-level parallel microprocessors . In this paper, we introduce the cyclic instruction processing of VL IW, which greatly enhances the execution speed of instructions and predicts the development of VL IW from one aspect.