用缓冲场效应晶体管逻辑(BFL)电路,研究了GaAs MES FET单片集成电路的工艺.为提高单片电路的集成度,给出了设计平面器件最小欧姆接触长度的直读曲线.对磷酸系腐蚀液的工艺特性进行了研究,并与其他几种常用的腐蚀液进行了比较.采用盐酸浸泡法结合栅区深腐蚀技术,明显地改善了肖特基势垒结的特性.利用俄歇能谱仪对Au-Ti-GaAs肖特基势垒结的热退化失效进行了分析,并提出了改善措施.已制出管芯平均传输时延小于100ps的GaAs单片集成门电路. The technology of GaAs MES FET monolithic integrated circuit is studied by using the BFL circuit. In order to improve the integration of the monolithic circuit, a direct reading curve is designed to design the minimum ohmic contact length of the planar device. The technological characteristics of the etching solution were studied and compared with other commonly used etching solutions.The hydrochloric acid immersion method combined with the gate etch-deep etching technique significantly improved the Schottky barrier junction characteristics.Using Auger energy The failure of thermal degradation of Au-Ti-GaAs Schottky barrier junction is analyzed and the improvement measures are proposed.A GaAs monolithic integrated gate with an average transmission delay of less than 100ps has been fabricated.