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当前,对计算机内存系统的研究内容集中优化内存请求访问队列,以达到充分利用现有的数据并行内存系统的带宽同时节省尽可能降低系统的能耗。由于DRAM芯片自身读写延迟的改进缓慢,优化的访存序列也很难得到满意的效果。本文通过在DIMM模块中加入预取机制,以掩盖DRAM芯片的读写延迟,并且依据访问序列的特性,动态调整预取块的大小,从而提升系统的平均存储响应时间。仿真分析证明,这种方案可以提升内存系统的存取效率。
Currently, research on computer memory systems focuses on optimizing memory request access queues so as to fully utilize the bandwidth of existing data parallel memory systems while saving the system energy consumption as much as possible. Due to the slow improvement of the DRAM chip’s own reading and writing delay, the optimized memory access sequence is also difficult to obtain satisfactory results. In this paper, the prefetching mechanism is added into the DIMM module to mask the read / write delay of the DRAM chip and dynamically adjust the size of the prefetch block according to the characteristics of the access sequence so as to improve the average storage response time of the system. Simulation analysis shows that this scheme can improve the memory system’s access efficiency.