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本文首先讨论了模拟极性比较法解调器,由此着手解释了对于4DPSK信号而言的数字式解调器。这种被称作为极性比较法数字式解调样机已制成。该实验样机在文中作了扼要叙述。除掉限幅器、滤波器和滤波器之前的电路外,该实验解调器由中小规模数字集成电路构成。为了能够估计极性比较法模拟解调器与相应的实验数字解调器的误码率性能差别,文章在可加高斯白噪声条件下,推证了四相相干检测和极性比较法检测的理论误码率。这里论证众所周知的四相相干检测误码率的目的是为了便于近一步导出4DPSK极性比较法解调器的误码率公式和曲线。实验指出,已制成的实验数字解调器实测误码率较为接近该理论误码率。
This article first discusses Analog Polarity Compare Demodulator, which explains the digital demodulator for 4DPSK signals. This is known as a polar analog digital demodulation prototype has been made. The experimental prototype in the text made a brief description. The experimental demodulator consists of small and medium scale digital integrated circuits except for the circuit before the limiter, filter and filter. In order to be able to estimate the bit error rate performance difference between the analog comparator demodulator and the corresponding experimental digital demodulator, the paper proves that the four-phase coherent detection and polarity comparison detection Theoretical bit error rate. Here to demonstrate the well-known purpose of the four-phase coherent detection bit error rate is to facilitate the near future derived 4DPSK polarity comparison demodulator bit error rate formula and curve. Experiments show that the measured bit error rate of the experimental digital demodulator is relatively close to the theoretical bit error rate.