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采用0.18μm CMOS工艺,设计了一种连续速率时钟与数据恢复(CDR)电路。该CDR电路主要由全速率鉴频鉴相器、多频带环形压控振荡器、电荷泵等模块组成。其中,全速率鉴频鉴相器不但具有很好的鉴频鉴相功能,而且结构简单,减小了功耗和面积。多频带环形压控振荡器不但调谐范围很宽,而且引入到环路中的调谐增益较低,解决了高振荡频率和低增益之间的矛盾问题。采用自举基准和运放的电荷泵减小了各种非理想因素的影响。仿真结果表明,该CDR电路版图尺寸为265μm×786μm,功能正常,且能恢复622~3 125Mb/s之间的伪随机数据;在1.8V电源电压下,输入伪随机速率为3 125Mb/s时,功耗为100.8mW,恢复出的数据和时钟的抖动峰峰值分别为5.38ps和4.81ps。
A 0.18μm CMOS process is used to design a continuous rate clock and data recovery (CDR) circuit. The CDR circuit is mainly composed of a full-rate phase frequency detector, a multi-band ring voltage controlled oscillator, a charge pump and other modules. Among them, the full-rate phase frequency detector phase not only has a good Kam phase Kam phase function, and the structure is simple, reducing power consumption and area. Multi-band ring VCO not only has a wide tuning range but also has a low tuning gain introduced into the loop, solving the problem of high oscillation frequency and low gain. The use of bootstrap reference and op amp charge pump reduces the impact of various non-ideal factors. The simulation results show that the layout size of the CDR is 265μm × 786μm with normal function and can restore pseudo-random data between 622 ~ 3 125Mb / s. When the pseudorandom data rate is 3 125Mb / s at 1.8V supply voltage , The power consumption is 100.8mW, the jitter peak value of the recovered data and clock are respectively 5.38ps and 4.81ps.