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充分利用有限冲击响应数字滤波器(Finite Impulse Response digital filter,FIR)系数的对称特性,借助于MAT-LAB语言和现场可编程门阵列(FPGA)实现了一种高效的低通滤波器。设计过程中通过简化的VHDL语言编写程序,实现了加减乘法运算,使用优化的CSD编码技术缩短了乘法器的运算时间,采用FPGA滤波器芯片和QuartusⅡ软件搭建仿真电路、用Matlab软件进行理论验证。实验结果基本符合理论值,验证了此种滤波器的实现方法简单,计算速度快,节省硬件资源,抗干扰能力强,灵活,性能优于传统的FIR滤波器。
Making full use of the symmetry characteristics of finite impulse response digital filter (FIR) coefficients, an efficient low-pass filter is implemented by means of MAT-LAB language and field programmable gate array (FPGA). In the design process, the program is simplified by VHDL language, and the addition and subtraction multiplication operations are realized. The optimized CSD coding technology is used to shorten the operation time of the multiplier. The FPGA circuit and Quartus Ⅱ software are used to build the simulation circuit, and the theory is verified by Matlab software . The experimental results are basically in line with the theoretical values, verifying that the implementation of the filter is simple, the calculation speed is fast, the hardware resources are saved, the anti-interference ability is strong, the flexibility is better, the performance is better than the traditional FIR filter.