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采用FPGA作为视频采集控制和图像处理芯片,配置NiosⅡ软核,在FPGA片内完成图像处理和图像显示控制,简化了硬件电路和软件程序的设计。在FPGA片内编写视频采集时序,并配置NiosⅡ控制软核,模拟视频数据经视频解码芯片输出ITU-RBT.656格式数据送入FPGA,通过时序控制和NiosⅡ软核把视频解码数据依序存储在SSRAM中,并进行裁剪、交织、颜色处理。
FPGA as a video capture control and image processing chip, Nios Ⅱ configuration soft-core, in the FPGA chip to complete the image processing and image display control, simplifying the hardware circuit and software design. In the FPGA chip to write video capture timing, and configure Nios Ⅱ control soft core, the analog video data output by the video decoder chip ITU-RBT.656 format data sent to the FPGA, through the timing control and Nios Ⅱ soft core video decoding data stored in sequence SSRAM, and cutting, interweaving, color processing.