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HDS-9是一台速度高(双处理机500万次/秒)、容量大(主存512K字),主要用于数据处理的计算机系统。此机在系统结构上采用多重处理机结构,流水线控制技术,虚拟存储器技术,存储器环状保护技术,存储器多模交叉访问,高速缓冲技术,RAS技术,统一标准接口的I/O系统;在工艺技术方面采用高密度组装技术,用SSI-TTL电路组成单臂门闩触发器系统;在系统软件方面采用匀称或平等的操作系统来处理多重处理机关系。 本文着重讨论了多重处理机结构,虚拟存储器,Cachc缓冲技术以及流水线控制技术有关方面问题和实施途径。
HDS-9 is a high speed (dual processor 500 million / sec), large capacity (main memory 512K words), mainly for data processing computer systems. This machine adopts multiprocessor structure, pipeline control technology, virtual memory technology, memory ring protection technology, memory multi-mode cross access, cache technology, RAS technology and unified standard interface I / O system in the system structure. Technical aspects of the use of high-density assembly technology, SSI-TTL circuit composed of single-arm latch trigger system; in the system software using symmetrical or equal operating system to handle multiple processor relationships. This article focuses on issues related to multi-processor architecture, virtual memory, Cachc buffering, and pipeline control techniques and implementation approaches.