Gate-grounded NMOS(gg NMOS) transistors have widely served as electro-static discharge(ESD)protection devices for integrated circuits. The layout strategy of gg NMOS greatly influences its ESD protection characteristics. Layout strategies forvariation of the number of substrate-pickup stripes are investigated in this paper. Direct current and transmission-line pulsing test results are presented to verify that adjustable holding voltages are accessed by variation of the number of substrate-pickup stripes. The design with two evenly distributed substrate-pickup stripes among different fingers is found to exhibit the highest second break current and optimal width-scaling characteristics. Gate-grounded NMOS (gg NMOS) transistors have widely served as electro-static discharge (ESD) protection devices for integrated circuits. Layout strategy for variation of the number of substrate-pickup stripes are investigated in this paper. Direct current and transmission-line pulsing test results are presented to verify that adjustable holding voltages are accessed by variation of the number of substrate-pickup stripes. The design with two evenly distributed substrate-pickup stripes among different fingers is found to exhibit the highest second break current and optimal width-scaling characteristics.