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提出了一种支持子字并行的乘法器体系结构,并完成了其VLSI设计与实现。该乘法器在16bit阵列子字并行结构的基础上,扩展了有符号与无符号之间的混合操作,采用多周期合并技术,实现了32bit宽度的子字并行,并支持子字模式的乘累加,同时采用流水线设计技术,能够在单周期内完成4个8×8、2个16×16或1个32×16的有符号/无符号乘法操作。0.18μm的标准单元库的实现表明该乘法器既能减小面积又能提高主频,是硬件消耗和运算性能的较好折衷,非常适用于多媒体微处理器的设计。
A multiplier architecture supporting subword parallelism was proposed and its VLSI design and implementation were completed. Based on the 16bit array subword parallel structure, the multiplier expands the mixed operation between signed and unsigned, and adopts the multi-cycle combining technique to realize the parallelism of subwords of 32bit width and supports multiply accumulate of subword mode While using pipeline design techniques to enable four 8x8, two 16x16, or one 32x16 signed / unsigned multiplication operations in a single cycle. The implementation of 0.18μm standard cell library shows that the multiplier can not only reduce the area but also increase the frequency, which is a good compromise between hardware consumption and computing performance. It is very suitable for the design of multimedia microprocessors.