A novel DSP to ASIC (Application Specific Integrated Circuit) architecture desig n methodology is presented in this paper for reducing power/area consumption. Traditional methods always focus on optimizing hardware structure or algorithm sep arately. The authors propose a new method called PRF (ParallelingReducing-Fol-ding) framework to combine hardware optimization with algorithm simplification. In the first step,paralleling, unfolding technology is applied to divide one data path into several channels and expose the redundancy of the algorithm. In the second step, reducing,decoupling theory is used to reduce computational complexity.In the last step, folding, timemultiplexing method is used to merge similar components. As an exoteric methodology framework, many optimization methods can be integrated into the PRF framework.To optimize a 3N taps FIR (Fincte Impact Response)and obtain a content result,PRF methodology framework is applied.