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设计了一种基于除2/除3级联技术的可编程整数分频器。通过对其结构上的修改,明显扩大了分频比范围。同时利用在高频段采用电流模式逻辑(CML)结构和在低频段采用改进的真单相时钟(TSPC)结构进行分频,提高了分频器的工作频率。最后,基于SMIC40nm CMOS工艺,采用Cadence Spectre工具进行仿真,该分频器能够在16～127的分频比范围内对频率范围为0.5～5GHz的输入信号进行正确分频,其版图面积为107×275μm。
A programmable integer divider based on divide-by-2 / divide-3 cascades is designed. Through its structural changes, it obviously expands the range of frequency division ratio. At the same time, the use of current mode logic (CML) in the high-frequency structure (CML) structure and improved low-frequency single-phase clock (TSPC) structure to improve the frequency divider. Finally, based on the SMIC40nm CMOS process, Cadence Specter was used to simulate the input signal frequency range of 0.5 ~ 5GHz in the range of 16 ~ 127. The layout area was 107 × 275 μm.