TSMC (Taiwan semiconductor Manufacturing Company) 20nm is considered as an extremely complex technology with many more design rules, more electrical variations and other factors to consider.In addition to this, the 20nm technology introduces new manufacturing process-DPT (Double Patterning Technology) which make it possible to use current lithography techniques to manufacture 20nm IC (integrated circuit) chips.But, the implementation of DPT and how to avoid DRC issues in current 20soc design are important issue worth considering.This paper mainly describes the application of DPT in full chip implementation of a specific design at the 20nm process that results in high performance and low power consumption.Techniques described of this paper can be leveraged for any SoC/ASIC (System on Chip/Application Specific Integrated Circuit) using 20nm SoC process.Applying these techniques, we achieved our goals of fast design cycles.