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提出一种改进的双控制通路锁相环结构。改进锁相环的两个控制通路有不同的压控振荡器增益。其中,粗调节通路的压控振荡器增益较大,用来调节锁相环的输出频率范围;细调节通路的压控振荡器增益较小,用来决定环路带宽,同时优化锁相环的抖动特性。电路芯片采用SMIC0.18μmCMOSLogic工艺加工。后仿真结果表明该锁相环的输出频率范围为600MHz到1.6GHz,并有良好的抖动特性。
An improved dual-control-path PLL architecture is proposed. The two control channels that improve the phase-locked loop have different voltage-controlled oscillator gains. Among them, the rough adjustment path voltage-controlled oscillator gain larger, used to adjust the output frequency range of the PLL; thin adjustment path of the VCO gain smaller, used to determine the loop bandwidth, while optimizing the phase-locked loop Jitter characteristics. Circuit chip using SMIC0.18μmCMOSLogic process. Post-simulation results show that the PLL output frequency range of 600MHz to 1.6GHz, and has good jitter characteristics.