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针对CAN协议中提出的串行CRC检验原理,给出其硬件实现方法及具体实现时应需注意的技术问题,给出了RTL级的VHDL代码。为了提高CRC编码的生成速度和CRC检验的效率,介绍了CRC检验的并行原理,并针对CAN协议中CRC编码的生成多项式推导出了8位并行CRC编码的逻辑关系式。最后对串行和并行两种实现方式进行了性能对比,并给出了为满足CAN协议而进行CRC编码时应注意的问题。
Aiming at the principle of serial CRC checking proposed in CAN protocol, the hardware implementation methods and the technical problems that should be noticed in the implementation are given. The VHDL code of RTL is given. In order to improve the generation speed of CRC codes and the efficiency of CRC checking, the parallel principle of CRC checking is introduced. And the logic relation of 8-bit parallel CRC codes is deduced according to the generating polynomial of CRC codes in CAN protocol. Finally, the performance comparison between serial and parallel implementations is given, and the issues that should be paid attention to when CRC coding is implemented to meet the CAN protocol are given.