提出了一种RLC互连树零时钟偏差构建方法.给出了RLC互连温度非均匀分布及其延时的解析公式,并推导计算了最优的零时钟偏差点,所提模型同时考虑了互连温度非均匀分布、电感效应及不对称互连结构对零时钟偏差点的影响.针对65nm工艺节点对所提模型进行了仿真验证,结果显示,相较于同类模型,最大误差不超过1%. A method to construct zero-clock bias of RLC interconnection tree is proposed.Analyzing the non-uniform temperature distribution and delay of RLC interconnection is given and the optimal zero-clock deviation point is deduced.The proposed model considers both The effect of non-uniform temperature distribution, inductance effect and asymmetric interconnect structure on the zero-clock deviation point is simulated.The simulation results show that the maximum error is less than 1 %.