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为研究可演化组合逻辑电路对静电放电的抗扰特性,提出了一种基于Cartesian模型和虚拟重配置技术的可演化组合电路系统模型,按照静电放电抗扰度测试标准IEC 61000-4-2分析了电路逻辑功能的受扰规律,归纳为单极性逻辑翻转和瞬态逻辑击穿2种故障模型。利用故障注入的方法模拟静电放电干扰环境,在故障节点比例逐渐增加的条件下进行了功能电路的演化设计试验。结果表明:当静电干扰事件较少时,演化电路可以快速稳定的演化生成功能完备的数字电路;当静电干扰事件频发且造成大量逻辑单元受扰时,其仍能演化生成适应度达0.9的功能电路。因此,可演化组合逻辑电路在逐渐恶劣的静电放电干扰环境下表现出高可靠的抗扰特性。
In order to study the anti-electrostatic characteristic of the combinational logic circuit against electrostatic discharge, an evolutionary combinational circuit system model based on Cartesian model and virtual reconfiguration technology is proposed. According to the standard of IEC 61000-4-2 The disturbing law of the circuit logic function is summarized as two kinds of fault models of unipolar logic flip-flop and transient logic breakdown. Fault injection method was used to simulate the electrostatic discharge interference environment, and the evolution design of the functional circuit was carried out under the condition of the increasing proportion of faulty nodes. The results show that evolving circuits can evolve quickly and steadily to generate fully functional digital circuits when there are few static disturbance events. When static disturbance is frequent and a large number of logic units are disturbed, evolutionary circuits can still evolve with a fitness of 0.9 Functional circuit. Therefore, evolutive combinational logic circuit in the gradual electrostatic discharge interference environment shows high reliability of anti-jamming characteristics.