许多十进计数器是用四个双稳态触发器加上反馈电路组成.这样,不但计数电路复杂,且因须对四个双稳态触发器译码,故读出电路亦复杂.本文所述2-5进制十进计数器方案没有上述麻烦,可建议在15兆赫以下的十进计数器中采用.图1表示出2-5进制十进计数器的方框图.“双稳”有两个状态,“五稳”有五个状态.两者级联起来有十个状态,刚好可作为十进计数器.图1还列出表示计数器计数时的次序. Many decimal counters are composed of four bistable flip-flops plus a feedback circuit, so that not only is the counting circuit complicated, but also because the four bistable flip-flops must be decoded, the readout circuit is complicated as well The 2-5 hexadecimal decadal counter scheme is free from the above inconveniences and may be recommended for use in decimator up to 15 MHz Figure 1 shows a block diagram of a 2-5 decagonal decimal counter. State, there are five states of the “five stable.” There are ten states cascaded together, just as a decimal counter Figure 1 also lists the order when counting the counter.