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为了提高接收器在多通道和多协议应用中的性能,提出了一种基于高线性度相位插值器的低抖动串行链路接收器。采用环形压控振荡器锁相环提供参考时钟,通过数字滤波器控制相位插值器调整采样时钟相位从而完成低抖动的数据恢复。整个接收器在65 nm CMOS工艺平台实现流片验证,单通道接收器的面积为320μm×685μm。测试结果表明,接收器工作在3.125 Gbit/s时,引入的总抖动仅为11.3 ps;电路采用1.2 V供电,功耗仅为21 m W;在PCIE,FC和SRIO三种协议规定的1.062 5~3.125 Gbit/s数据率下,收发器的误码率均小于10-12。
In order to improve the receiver performance in multi-channel and multi-protocol applications, a low-jitter serial link receiver based on high-linearity phase interpolator is proposed. Using a ring voltage controlled oscillator phase-locked loop to provide a reference clock, the digital filter control phase interpolator to adjust the sampling clock phase to complete the low jitter data recovery. The entire receiver in the 65 nm CMOS technology platform to achieve flow-chip verification, single-channel receiver area of 320μm × 685μm. The test results show that when the receiver operates at 3.125 Gbit / s, the total jitter introduced is only 11.3 ps; the circuit uses 1.2 V power supply and the power consumption is only 21 mW; in the PCIE, FC and SRIO protocols 1.062 5 ~ 3.125 Gbit / s data rates, the transceiver bit error rate of less than 10-12.