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基于部分耗尽型绝缘层上硅(SOI)器件的能带结构,从电荷堆积机理的电场因素入手,为改善辐照条件下背栅Si/SiO_2界面的电场分布,将半导体金属氧化物(MOS)器件和平板电容模型相结合,建立了背栅偏置模型.为验证模型,利用合金烧结法将背栅引出加负偏置,对NMOS和PMOS进行辐照试验,得出:NMOS背栅接负压,可消除背栅效应对器件性能的影响,改善器件的前栅I-V特性;而PMOS背栅接负压,则会使器件的前栅I-V性能恶化.因此,在利用背栅偏置技术改善SOI/NMOS器件性能的同时,也需要考虑背栅偏置对PMOS的影响,折中选取偏置电压.该研究结果为辐照条件下部分耗尽型SOI/MOS器件背栅效应的改善提供了设计加固方案,也为宇航级集成电路设计和制造提供了理论支持.
Based on the band structure of partially depleted silicon-on-insulator (SOI) devices, starting from the electric field of charge accumulation mechanism, in order to improve the electric field distribution of the back gate Si / SiO 2 interface under irradiation conditions, the semiconductor metal oxide ) Devices and flat-panel capacitance model, a back-gate bias model was established.In order to verify the model, the back-gate was induced to be negative-biased by alloy sintering method, and the NMOS and PMOS were tested for irradiation. Negative voltage can eliminate the effect of backgate effect on the device performance and improve the front gate IV characteristics of the device, while the PMOS back gate negative voltage will deteriorate the front gate IV performance of the device.Therefore, To improve the performance of SOI / NMOS devices, we also need to consider the influence of the back-gate bias on the PMOS and select the offset voltage in a compromise. The result of this study is to provide the improvement of the back-gate effect of partially depleted SOI / MOS devices under irradiation The design and reinforcement program, but also for the spacecraft IC design and manufacturing provides a theoretical support.