当前半导体集成电路芯片制造技术已经可以在一个芯片上集成数千万只晶体管,并且继续按照摩尔法则的规律向前发展。 但是,伴随着芯片向深亚微米级进军,正确有效地实现芯片的逻辑设计与物理设计的困难也显得越来越突出。如何让众多集成在芯片上的晶体管组成正确的异常复杂的系统,实现预期的越来越强大的功能,而且付出的人力、物力代价尽可能低,进入市场的周期时间尽可能短?这就是今 The current semiconductor integrated circuit chip manufacturing technology has been integrated in a chip tens of millions of transistors, and continue to follow the laws of Moore’s law to move forward. However, with the chip to enter the deep submicron level, the difficulty of the correct and effective realization of the logic design and physical design of the chip becomes more and more prominent. How to make a large number of integrated transistors on the chip form the correct abnormal complex system to achieve the expected more and more powerful features, but also pay the human and material costs as low as possible, the market cycle time as short as possible? This is today